The increasing demand for low cost, miniaturized, power efficient communication systems is driving demand for higher levels of functionally to be incorporated within integrated circuits. Phase-locked loop circuits are not immune to these demands. A phase-locked loop (PLL) is a circuit that maintains a signal in a fixed phase relationship to another signal, known as the reference signal. A type of closed-loop feedback control system, PLLs may be dispersed throughout a design to support various system functions.
A PLL circuit may consist of a reference signal, a phase detector and a voltage-controlled oscillator (VCO), arranged in a negative feedback configuration. Additionally, a filter, a charge pump, and a divider may be present. The VCO generates a periodic output signal that is fed back into the phase detector (or, alternatively, a phase frequency detector). When the output signal is not phase-aligned with the reference signal, the phase detector sends a pulse to the VCO (or intervening circuitry), causing the frequency of the output signal to change. The frequency shift persists until the phase of the output signal is back into alignment with the reference. In reality, the frequency shift will not be instantaneous, and will result in an overshoot of the phase correction. Eventually, the phase and frequency of the loop will both settle to the correct value, but there will be several perturbations back and forth of the relative phase of the reference and output signal.
In FIG. 1, for example, a graph shows a voltage over time, which may represent the analog voltage fed into the VCO of the PLL circuit. At a time, t1, the voltage changes from a steady-state voltage to a voltage greater than the steady-state voltage; at time t2, the voltage crosses the steady-state voltage line and is less than the steady-state voltage; at time, t3, the voltage again crosses the steady-state voltage and is greater than the steady-state voltage. The voltage thus oscillates across the steady-state voltage, until finally achieving the steady-state voltage at approximately time, t11.
The PLL circuit design involves two competing phenomena: locking speed and jitter. The locking speed is how fast the PLL is able to lock the output signal to the reference signal litter is a variation of the signal over time, and may include phenomena such as signal skew and coupled noise. The bandwidth of the PLL, a process variant parameter, together with the VCO phase noise and the reference chain noise, determines what the locking speed and the jitter of the PLL will be. A PLL with a high loop bandwidth provides a fast lock time; however, jitter on the reference signal passes through to the output signal with little or no attenuation. A PLL with a low loop bandwidth filters out the jitter in the reference signal, but is slower to lock the output signal to the reference signal. Such a PLL will also not attenuate the phase jitter of the VCO by much. Knowing the PLL loop bandwidth may facilitate the design of the PLL, whatever the system requirements.
Some PLL designs place tight restrictions upon the tolerance of the PLL components. This ensures that the PLL loop bandwidth falls within an acceptable window. Component variables within the PLL that contribute to PLL closed loop bandwidth include the tuning sensitivity of the VCO, component values of the loop filter, values programmed Into the feedback divider, and the gain of the phase detector (or phase frequency detector) and the charge pump. Some prior art designs rely upon schemes such as injecting test signals into strategic circuit nodes and measuring the resultant sidebands at the PLL output.